The client hands-off the RTL along with the timing related specifications and CoreEL would take the design from synthesis to prototype, with an optional sign-off at GDSII stage.

This service involves:

	Floor planning.
	Layout.
	Routing.
	Timing closure with client's assistance.

This service also extends to physical verification, extraction and LVS for GDSII sign-off to the foundry.

Testability Services (DFT)

We specialize in testability implementation for our esteemed client. Using industry standard Mentor Graphics tool flow and in depth understanding of the methodology, CoreEL has helped its client achieve first time silicon success with its DFT services.

Executed as a low client-involvement project, could be carried-out at client's site or off-site. CoreEL would participate with the client for:

	Testability, architecture for DFT friendly designs.
	Scan Insertion.
	ATPG.
	Memory Bist.
	IEEE1149.1 and Boundary Scan.
	ATPG library development and coverage analysis.

We provide Consulting as a value add Service to our clients and this would help them grade their test bench to improve test coverage. In several cases, our consultants have helped improve the fault coverage from 90% to over 98%.

In addition, we offer ATPG for scan inserted Netlists covering,

	Stuck at fault model.
	Transition fault model (At-Speed).
	Path delay fault model (At-Speed).
	Pseudo stuck-at fault model (IDDQ Test).

We offer RTL verification services. Starting with clients design documents and the RTL, our verification methodology enables lead time by developing robust environment. The numbering based test bench system ensures that all corner cases of the design are uncovered and provides traceability to the features being verified. The numbering based test bench system ensures that all corner cases of the design are uncovered and provides traceability to the features being tested; this methodology has proven to yield very high coverage. Linting provides the Design Rule Check and acts as a metric for adherence to coding guidelines.

This service is particularly suited for verification of Processors and Microcontroller designs wherein each instruction has to be thoroughly tested for machine cycle accuracy. Robust verification methodology becomes critical while ensuring that dependencies are met during execution of a sequence of instructions in a pipelined architecture. This methodology has been perfected over several processor architectures developed and is being offered as a service to its customers.

Further, the methodology provides for an equivalence check (Formal Verification) at various stages of the engineering flow such as:

	RTL to RTL.
	RTL to Gate Level Netlist.
	Netlist to Netlist.

As a part of the verification services, we offer Physical verification service, which involves,

	Design Rule Checks (DRC) against the foundry rule decks.
	Layout Vs Schematic (LVS) checks.
	Parasitic extraction.

The verification process is iterative and is executed with tight interaction with the clients. CoreEL uses Mentor Graphics Calibre and Calibre xRC, industry standard tools for GDSII tape-out.