CoreEL’s H.264 decoder design implementation is a highly pipelined architecture for faster macro-blocks processing. The decoder is easily portable across various FPGA platforms. The IP core has been validated with ITU and Fraunhofer test streams on our custom built hardware board called Rosebud, based on Xilinx Virtex-5 FPGA device.

The decoder design is fully autonomous and does not require external host processor for decoder to perform. The decoder solution is available both as FPGA netlist and Source code.

Apart from the H.264 IP core, DDR2 controller, Ethernet controller and Display controller is also available. The core can also be customized according to the customer requirements.