We live in an information age; one characterized by an ever growing consumption of digital multimedia content. Propelled by the digital revolution, consumption of high definition video content is exponentially growing.

The professional video &broadcast industry is under immense pressure to deliver Hi-Defcontent with the least bandwidth consumption. The solution for this concern is the adoption of the right compression/decompression standard that does not compromise on the quality of the video yet can be broadcasted over a bandwidth constrained network.

Over the years, the H.264 has emerged as the as the de-facto standard for the hi-def video encoding industry. Some of the plausible reasons include,

• Multiple reference pictures
• Intra / Inter Picture prediction
• Motion compensation / estimation
• Temporal & Spatial coding techniques
• MBAFF / PicAFF
• De-blocking
• Entropy coding – CABAC / CAVLC
• Network Abstraction Layer (NAL)

CoreEL has developed a host of Digital Video IPs. These encoder and decoder cores are single chip FPGA based solution.

• The cores are optimized to deliver the highest performance while minimizing the latency through the system.
• They cores are designed to be scalable to support higher bit rates and resolutions.
• The designs are fully autonomous and do not require an external processor to aid the operations.
• The solutions have been implemented on a single FPGA device and extend flexibility to customize for specific applications.
• The core supports Elementary Streams (ES) and optionally Transport Streams (TS)
• The decoder core can provide the video output either in decode order or optionally in display order
• The cores are currently available on Kintex-7, Virtex-5, Virtex-6, Spartan-6, Arria V, Arria II GX, Cyclone-3 and Cyclone-4 devices

Our IP cores are mainly targeted for following applications: