Proficient in VHDL/Verilog RTL Coding, System C/System Verilog.
Knowledge of C and Scripting using PERL, TCL/TK.
Proficient knowledge of FPGA’s and related devices and Timing Analysis.
Good in FPGA Synthesis & PAR Tools.
Proficient in Simulation tools like Modelsim, Questasim, and FPGA tools.
Experience in Test Plan Definition, Coverage Driven Verification, Test Bench Development
& Functional Modelling.
Knowledge of MS Project.
Signal processing knowledge is desirable.
Soft Skills
Good presentation skills.
Excellent group work skills
Possess good interpersonal and Communication skills
Major Tasks and Responsibilities
Given an architecture, create work breakdown structure & understand effort estimations.
Get the designs implemented and/or executed.
Create module levels details from architecture, coding, simulation and perform peer
review. Apply the methodologies for design, verification and validation.
Create and maintain design documents and user manuals.
Do performance analysis and dependency analysis of the design.
Supervise and mentor 2 Design Engineers. Act as a TL in the absence
of supervisor.
Participate in Conference calls and discussions with customers.
