5-day Faculty Development Program on “FPGA Design Flow with Vivado and 7-series boards”

A 5-day Faculty Development Program on “FPGA Design Flow with Vivado and 7-series boards” was held from 6th September to 10th September 2016 at CoreEL Technologies, Bangalore office. The program was attended by faculty and research scholars from institutes and universities across India, including IIT-Indore, NITs, JNTUA, University of Calcutta, Mumbai and VTU. The faculty person for the program was Mr. Balachander Harinath, Manager-FAE, CoreEL University Program.
The hands-on program included the following topics:
• Vivado Design Flow
• Synthesizing and Implementing an RTL Design
• Using the IP Catalog
• Xilinx Design Constraints
• Hardware Debugging
• Adding Peripherals in Programmable Logic
• Creating and ADding your own Custom IP
• Writing Basic Software Applications
• Software Debugging using SDK
• Vivado System Generator
• Designing an FIR Filter and Image Processing Applications
The program was well received by the participants. During the valedictory program, Ms. Sadiya Arshad, National Manager, CoreEL University Program, presented all participants with a certificate and memento, along with discount coupons for product and training programs conducted by CoreEL.

FDP original